24.03.24 | Vollzeit | Villach | Infineon Technologies AGOf experience in mixed signal IC design/layout/verification or support - Programming skills C, Perl, Tcl, SKILL (Cadence) - Knowledge of design languages System Verilog or VHDL - Experience with Unix/Linux and Compute Farm environment (e.g. Load Sharing Facility/LSF) - Hands-on with some mixed-signal EDA
Später ansehen24.03.24 | Vollzeit | Villach | Infineon Technologies AGOf experience in mixed signal IC design/layout/verification or support • Programming skills C, Perl, Tcl, SKILL (Cadence) • Knowledge of design languages System Verilog or VHDL • Experience with Unix/Linux and Compute Farm environment (e.g. Load Sharing Facility/LSF) • Hands-on with some mixed-signal EDA
Später ansehen24.03.24 | Vollzeit | Villach | Infineon Technologies AGOf experience in mixed signal IC design/layout/verification or support - Programming skills C, Perl, Tcl, SKILL (Cadence) - Knowledge of design languages System Verilog or VHDL - Experience with Unix/Linux and Compute Farm environment (e.g. Load Sharing Facility/LSF) - Hands-on with some mixed-signal EDA
Später ansehen24.03.24 | Vollzeit | Villach | Infineon Technologies AGOf experience in mixed signal IC design/layout/verification or support - Programming skills C, Perl, Tcl, SKILL (Cadence) - Knowledge of design languages System Verilog or VHDL - Experience with Unix/Linux and Compute Farm environment (e.g. Load Sharing Facility/LSF) - Hands-on with some mixed-signal EDA
Später ansehen29.03.24 | Teilzeit | Klagenfurt am Wörthersee, Vill | technikstellen.atFor this task if you have - A university bachelor or master degree in Electrical Engineering, Computer Science or equivalent - At least 3 years of experience in mixed signal IC design/layout/verification or support - Programming skills C, Perl, Tcl, SKILL (Cadence) - Knowledge of design languages System
Später ansehen18.03.24 | Vollzeit | www.steirerjobs.atInterface IPs - Experience with Cadence analog design tools - Expertise in S-parameters is a big plus - Knowledge of SystemVerilog is a plus - Fluent English language skills, German as a plus We offer competitive salaries and additional benefits based on your performance, experience and qualification
Später ansehen14.03.24 | Vollzeit | Wien | IXOS SOFTWARE Austria GmbHTeam of sales leaders and representatives to drive performance and exceed sales goals. · Define clear cadences and provide regular performance feedback and coaching to sales team members to help them reach their full potential. · Develop a data driven culture across the team from pipeline analysis
Später ansehen11.03.24 | Vollzeit | Villach | Infineon Technologies AGOf experience in analog mixed signal circuit design, with focus on clocking and high speed interface IPsExperience with Cadence analog design toolsExpertise in S-parameters is a big plusKnowledge of SystemVerilog is a plusFluent English language skills, German as a plusWe offer competitive salaries
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11.03.24 | Vollzeit, Freelancer, Teilzeit | Graz | Infineon Technologies AGAdditionally offerA basic understanding of SMPS and have knowledge of programmingA strong interest in integrated circuit design and layoutPrior experience with the Cadence design frameworkExcellent analytical thinking skillsCommunication skills in both English and/or GermanThis position is subject
Später ansehen11.03.24 | Vollzeit | Villach | Infineon Technologies AGAuf Blockebene, welche später in unterschiedlichsten Produkten weltweit zum Einsatz kommenZeichnen von Chip-Layout mit state-of-the-art CAD Software (Cadence)Überprüfung der erstellten Layouts auf Fertigbarkeit, ESD Festigkeit, mentation der durchgeführten ArbeitenFortlaufende Weiterbildung
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