13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
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13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
Später ansehen13.05.25 | Vollzeit | Villach | Infineon Technologies AGUsing constraint random and/or formal methodology - Good knowledge of SystemVerilog and UVM as well as scripting languages (e.g. Python, Perl, tcsh) - Knowledge of mixed-signal verification (as an advantage) - The ability to lead and develop fellow engineers - Fluent English skills and German as a plus
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